Delhi’s draft chip policy targets design, R&D and advanced packaging

Delhi’s proposed semiconductor policy would focus on chip design, research and advanced packaging rather than the large wafer-fabrication plants that need substantial land and water.

The 2026–31 draft sets out an indicative budget of ₹63–79 crore, with ₹1 crore proposed as seed funding in 2026–27. It aims to attract investment in fabless chip design, research and development, and assembly, testing, marking and packaging (ATMP) and outsourced semiconductor assembly and test (OSAT) facilities.

For eligible ATMP/OSAT and compound-semiconductor projects, the proposal includes an additional capital subsidy worth 50% of central assistance, capped at ₹50 crore per project. Other proposed support includes five years of lease-rental subsidy, exemptions on stamp duty and electricity duty, and a ₹2-per-unit power-tariff subsidy.

Chip-design startups and MSMEs could receive reimbursement of 20% of eligible design expenditure, capped at ₹15 crore per unit. The policy targets at least two commercialised indigenous chip designs from Delhi-based startups each year, while encouraging talent from IIT Delhi, IIIT Delhi, Delhi Technological University and Netaji Subhas University of Technology to work in the city.

IT minister Pankaj Singh said the government plans to place the policy in the public domain by the end of September after Cabinet approval.