IIT Delhi team demonstrates programmable micro-GPU prototype

Nammi Akash and Ravi Teja, MTech students at IIT Delhi, have led the development of a programmable micro-GPU for embedded visual systems rather than high-end computing hardware.

The Electrical Engineering Department team demonstrated graphics rendering through a custom floating-point GPU engine built in register-transfer language and mapped it to a Spartan-7 field-programmable gate array. Professors Jayadeva and Kaushik Saha guided the project.

IIT Delhi said the architecture could support industrial-control displays, low-cost human-machine interfaces, e-rickshaw dashboards, navigation terminals for small fishing boats and educational e-book readers. It can be adapted for application-specific integrated circuits or programmable hardware such as FPGAs.

The researchers plan to explore an 8-to-16-core vector-style graphics processor, alongside a compiler and graphics software toolchain. They are also working towards a proof of concept using a 65 nm ASIC process node and are seeking funding for ASIC development, system integration and commercialisation.